Similar to manual logic optimization, electronic design automation tools also need specific algorithms (such as Quinn McCluskey algorithm) to simplify the logic functions defined by designers. The files input into the automatic synthesis tool include register transfer level hardware description language code, process library (which can be provided by a third-party wafer foundry service organization) and design constraint files. These files may have different formats in different electronic design automation toolkit systems. The logic synthesis tool will generate an optimized gate level netlist, but the netlist is still based on the hardware description language. The routing of the netlist in the semiconductor chip will be completed in the physical design. Selecting process libraries corresponding to different devices (such as ASIC or FPGA) for logic synthesis, or setting different constraint strategies during synthesis, will produce different synthesis results.

The logical division of register transfer level code for design items, language structure style and other factors will affect the efficiency of netlist after synthesis. Most mature synthesis tools are based on register transfer level description, while advanced synthesis tools based on system level description are still in the development stage. Formal equivalence check in order to compare the equivalence between gate level netlist and register transfer level, formal equivalence check (formal verification) can be completed by generating such ways as irreducible satisfiability and binary decision diagram. In fact, the equivalence check can also check the logical equivalence between two register transfer level designs or between two gate level netlists. Timing analysis the clock frequency of modern integrated circuits has reached the megahertz level, and the timing relationship between a large number of modules and modules is extremely complex. Therefore, in addition to verifying the logic function of the circuit, timing analysis is also required, that is, check the delay of the signal on the transmission path to judge whether it matches the timing convergence requirements. The logic gate standard delay format information required for timing analysis can be provided by the standard unit library (or the timing information extracted from the unit designed by the user). With the continuous reduction of circuit feature size, the proportion of interconnect delay in the actual total delay becomes more and more significant. Therefore, after the physical design is completed, the timing analysis can be carried out accurately by taking the interconnect delay into account. After the physical design logic synthesis is completed, by introducing the process information provided by the device manufacturing company, the previously completed design will enter the layout planning, layout and wiring stage. Engineers need to reasonably set the parameters of the physical design tool and continuously debug according to the constraint information of delay, power consumption and area, so as to obtain the configuration, This determines the physical location of the component on the wafer. If it is a fully customized design, engineers also need to carefully draw the integrated circuit layout of the unit and adjust the transistor size, so as to reduce power consumption and delay.